Question

1. Design an FSM for divisibility by 3 tester decimal number.

Answer 1

Answer:

If the Finite State Machine is in State 0, then the input number is divisible by 3. If the FSM is in State 1 or State 2, then the input number is not divisible by 3. This FSM can be implemented using digital logic circuits, such as combinational logic and flip-flops.

Explanation:

An FSM, or Finite State Machine, can be designed to test the divisibility of a decimal number by 3. Here's one possible design:

There will be three states in the FSM, representing the remainder of dividing the input number by 3. The states will be labeled as follows:

State 0: The input number is divisible by 3 (remainder 0)

State 1: The input number has a remainder of 1 when divided by 3

State 2: The input number has a remainder of 2 when divided by 3

The FSM will start in State 0. For each decimal digit of the input number, the FSM will transition from one state to another, based on the value of the digit.

If the input digit is 0 or 3, the FSM will stay in State 0.

If the input digit is 1 or 4, the FSM will transition from State 0 to State 1.

If the input digit is 2 or 5, the FSM will transition from State 0 to State 2.

If the input digit is 6 or 9, the FSM will transition from State 1 to State 2.

If the input digit is 7 or 0, the FSM will stay in State 1.

If the input digit is 8 or 1, the FSM will transition from State 2 to State 0.

After all digits of the input number have been processed, if the FSM is in State 0, then the input number is divisible by 3. If the FSM is in State 1 or State 2, then the input number is not divisible by 3.

This FSM can be implemented using digital logic circuits, such as combinational logic and flip-flops.

To know more about the concept please go through the links:

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