Question

1.Which of the following statement is true for high impedance nodes ?
A. May be modeled as a open circuit B. May be modeled as a closed circuit C. These nodes can be verified by voltage measurement alone D. They are not floating nodes

2. Assuming Wn and Wp to be widths of the NMOS and PMOS transistors of a Domino CMOS Logic, the value of tPHL (high-to-low propagation delay) is equal to
A. Wn/Wp B. Wp/Wn C. Zero D. Wn + Wp

3.For a 180 nm process the value of the unit delay is approximately
A. 100 ps B. 12 ps C. 35 ps D. 55 ps

4. If the output and the input capacitance of logic is Cout and Cin respectively then the value of electrical effort is
A. Cin /Cout B. Cout /Cin C. 2Cin /Cout D. 2Cout /Cin

5. Find the value of the logical effort of a NOR-2 gate whose delay is equivalent to a CMOS inverter whose Wp/Wn = 3/1, where Wp and Wn are the widths of the PMOS and NMOS respectively
A. 5/3 B. 7/3 C. 11/5 D. 7/4

6. A NAND-2 gate drives a NOR-2 gate of equal dimensions and capacitive loading, then the logical effort of the compound network will be
A. 20/9 B. 25/3 C. 30/7 D. 35/7

7. For a three stage digital logic design using NAND, NOR and MUX, in series, the total parasitic delay is 8 unit and the best stage effort is 6. The total delay from primary input to output is
A. 27 B. 25 C. 26 D. 21

8. The frequency of an N stage ring oscillator with the following parameters: Logical effort = Branching Effort = Electrical Effort = parasitic delay = 1 units and delay = 3 units is A. 1/4N B. 4N C. 6N D. 1/6N

9. The time before the rising/falling clock edge till which the data must be stable for proper sampling of the data is referred to as
A. Set-up Time B. Hold Time C. Clock Period D. Tc-q delay

10. Memories based on positive feedback falls under the class of
A. Astable Circuits B. Bistable Circuits C. Multivibrators D. Dynamic Circuits

Answer 1

Answer :-

1.Which of the following statement is true for high impedance nodes ?

A.1 - A. May be modeled as a open circuit

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2. Assuming Wn and Wp to be widths of the NMOS and PMOS transistors of a Domino CMOS Logic, the value of tPHL (high-to-low propagation delay) is equal to

A.2 - D. Wn + Wp

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3.For a 180 nm process the value of the unit delay is approximately

A.3 - B. 12 ps

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4. If the output and the input capacitance of logic is Cout and Cin respectively then the value of electrical effort is

A.4 - B. Cout /Cin

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5. Find the value of the logical effort of a NOR-2 gate whose delay is equivalent to a CMOS inverter whose Wp/Wn = 3/1, where Wp and Wn are the widths of the PMOS and NMOS respectively

A.5 -  D. 7/4

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6. A NAND-2 gate drives a NOR-2 gate of equal dimensions and capacitive loading, then the logical effort of the compound network will be

A.6 - A. 20/9

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7. For a three stage digital logic design using NAND, NOR and MUX, in series, the total parasitic delay is 8 unit and the best stage effort is 6. The total delay from primary input to output is

A.7 - C. 26

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8. The frequency of an N stage ring oscillator with the following parameters: Logical effort = Branching Effort = Electrical Effort = parasitic delay = 1 units and delay = 3 units is A.

A.8 - D. 1/6N

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9. The time before the rising/falling clock edge till which the data must be stable for proper sampling of the data is referred to as

A.9 - A. Set-up Time

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10. Memories based on positive feedback falls under the class of

A.10 - B. Bistable Circuits