2) How do you represent wire crossing without. Jarmo
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Older electrical schematics showed connecting wires crossing, while non-connecting wires “jumped” over each other with little half-circle marks. Newer electrical schematics show connecting wires joining with a dot, while non-connecting wires cross with no dot. However, some people still use the older convention of connecting wires crossing with no dot, which may create confusion.For this reason, I opt to use a hybrid convention, with connecting wires unambiguously connected by a dot, and non-connecting wires unambiguously “jumping” over one another with a half-circle mark. While this may be frowned upon by some, it leaves no room for interpretational error: in each case, the intent is clear and unmistakable:
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Hey there,
I’m Siddhant.
Let me answer your question.
So, Quantum-dot cellular automata, as the successor of metal-oxide semiconductor field-effect transistors, are one of the promising nanotechnology devices, which have attracted myriad researchers in the recent decade. In this technology, coplanar wire crossing is one of the unique specifications that can reduce its reliability. In the present study, a heuristic method is introduced using the Karnaugh-Map (K-Map) to minimise the number of wire crossing as the first step. Afterwards, it attempts to replace each wire crossing with three non-wire crossing XOR gates that reduce all wire crossings to zero as the second step. Experimental results reveal that, reducing wire crossings to zero, the authors method for 3-variable functions lowers the number of gates about 54, 42, 58 and 59%, respectively, in comparison with K-Map, Genetic, Gate-Optimise and Universal Quantum-dot Cellular Automata Logic Gate (UQCALG) methods. For 4-variable functions, their method decreases the number of gates almost 64 and 58%, respectively.
Hope this answers your question.
I’m Siddhant.
Let me answer your question.
So, Quantum-dot cellular automata, as the successor of metal-oxide semiconductor field-effect transistors, are one of the promising nanotechnology devices, which have attracted myriad researchers in the recent decade. In this technology, coplanar wire crossing is one of the unique specifications that can reduce its reliability. In the present study, a heuristic method is introduced using the Karnaugh-Map (K-Map) to minimise the number of wire crossing as the first step. Afterwards, it attempts to replace each wire crossing with three non-wire crossing XOR gates that reduce all wire crossings to zero as the second step. Experimental results reveal that, reducing wire crossings to zero, the authors method for 3-variable functions lowers the number of gates about 54, 42, 58 and 59%, respectively, in comparison with K-Map, Genetic, Gate-Optimise and Universal Quantum-dot Cellular Automata Logic Gate (UQCALG) methods. For 4-variable functions, their method decreases the number of gates almost 64 and 58%, respectively.
Hope this answers your question.
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