Question

3. Draw a 4-bit dynamic shift register using Depletion load based nMOS inverter and pass transistor
and draw a table showing the stored data XXXX shifting towards the right side. Design should
assure the clocking of inputs with nonoverlap clock. (Hint: Consider your ID, for example
2018P3PS0123U. XXXX represents the 4-bit binary number of highest number among 0123.​

Answer 1

Answer:

sorry I didn't know how to draw on it