Question

5. A computer has l1 and l2 caches; the cache block consists of 8 words. Assume that the hit rate is the same for both caches and that it is equal to 0.95 for instructions and 0.90 for data. Assume also that the times needed to access an 8-word block in these caches are c1=1 cycle and c2=10cycles. A. What is the average memory access time experienced by the processor.

Answer 1

Answer:

red and then we can talk about it later I have the time to do it Mam and the people you know what time the game and the class and the teacher is really rough time and then we can talk about it later but I'll be in touch when I get ready