Question

53: Consider the circuit shown in the figure below. The
complete biasing of the MOSFET is not shown for simplicity
but it can be taken as a fact that My is switched ON for
positive value of Vin greater than 3.2 V with Ids(on) = 0.
When My is switched OFF then the value of rds = 00. A D.C.
current source is also connected across the MOS transistor.
Assuming Vc has negligible ripple voltage. If the source Vin
has a duty cycle of D, then the value of Vc after 5 input pulse
will be (Assuming Resistance R to be very large)
A
10V
M)
PD:
5 V
1.
V
3485315457
(51/C)DT
-(51/C)DT
(51/C)(1-D)T
-(51/C)(1-DT​

Answer 1

Collector supply voltage, VCC = 6 V

Collector load, RC = 2.5 kΩ

(i) We know that for faithful amplification, VCE should not be less than 1V for silicon transistor.

∴ Max. voltage allowed across RC = 6 − 1 = 5 V

∴ Max. allowed collector current = 5 V/RC = 5 V/2.5 kΩ = 2 mA

Thus, the maximum collector current allowed during any part of the signal is 2 mA. If the collector current is allowed to rise above this value, VCE will fall below 1 V. Consequently, value of β will fall, resulting in unfaithful amplification.

(ii) During the negative peak of the signal, collector current can at the most be allowed to become zero. As the negative and positive half cycles of the signal are equal, therefore, the change in collector current due to these will also be equal but in opposite direction.

∴ Minimum zero signal collector current required = 2 mA/2 = 1 mA

During the positive peak of the signal [point A in Fig. 1(ii)], iC = 1 + 1 = 2mA

And during the negative peak (point B), iC = 1 − 1 = 0 mA