Question

6. Using switch model derive propagation delay of a CMOS Inverter.
7. Compare digital logic performance metrics of NMOS logic/inverter with CMOS logic
designs in a tabular format with 3-4 minimum differences.
8. Summarize the different components present in the total Load capacitance of a static
CMOS inverter.
9. In the CMOS Inverter performance analysis you have performed, summarize your key
observations from VDD scaling along with simple plots.
10. In the CMOS Inverter performance analysis you have performed with Wp/Wn
variations, summarize your key observations with simple plots.
11. For a supply voltage of 2.5 V, the normalized on-channel resistances of NMOS and
PMOS transistors equal 13 k Ω and 31 kΩ, respectively. From the layout, we determine
the (W/L) ratios of the transistors to be 1.5 for the NMOS, and 4.5 for the PMOS. Cint
= 3.0 fF, Cext = 3.15 fF. What scaling factor allows us to get within 10% of the optimal
performance (intrinsic performance).
12. In order to drive a large capacitance (CL = 100 pF) from a minimum size gate (with
input capacitance Ci = 25fF), (a) you decide to introduce a four-staged buffer. Assume
that the propagation delay of a minimum size inverter is 50 ps. Also assume that the
input capacitance of a gate is proportional to its size. Determine the sizing of the four
additional buffer stages that will minimize the propagation delay. (b) If you could add
any number of stages to achieve the minimum delay, how many stages would you
insert? What is the propagation delay in this case? (c) Describe the advantages and
disadvantages of the methods shown in (a) and (b).
13. Derive the Dynamic power consumption relation for a CMOS Inverter/logic.
14. What are the important components and significance of power consumption of a static
CMOS logic?
15. For a chip composed of a logic with an average activity factor of 0.25, you are using a
standard cell process with an average switching capacitance of 25 pF/µm2
. The leakage
current per unit drain area typically is 100 pA/mm2
at room temperature. For a chip
with 1 billion gates, each with a drain area of 1.5 mm2 , the maximum short circuit path
current is 1mA/ µm2
and duration for which both PMOS and NMOS devices ON
simultaneously is around 0.1ns. Estimate the dynamic power, static power and short
circuit power and total power consumption of your chip if it has a total area of 70 µm2
and runs at 1GHz at VDD = 1.0 V.
16. As a rule of thumb, the Fanout 4 (FO4) delay for a process (in picoseconds) is 1/3 to
1/2 of the drawn channel length (in nanometers). Design a CMOS ring oscillator which
has a frequency of 1.5 G Hz in a 45 nm process.

Answer 1

Answer:

go through the attachment..