8 bit parallel adder of verilog description
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Answered by
0
module adder8bit_task4bit(a,b,cin,sum,co);
input [7:0]a,b;
input cin;
output reg [7:0]sum;
output reg co;
reg cint;
task task4bit;
input [3:0]a_task, b_task;
input cin_task;
output [3:0]sum_task;
output co_task;
{co_task,sum_task}=a_task + b_task + cin_task;
endtask
always@(*)
begin
task4bit(a[3:0], b[3:0], cin, sum[3:0], cint);
task4bit(a[7:4], b[7:4], cint, sum[7:4], co);
end
endmodule
Test bench
`timescale 1ns/1ps
module test_adder8bit;
reg [7:0]a,b;
reg cin;
wire [7:0]sum;
wire co;
adder8bit_task4bit add_task(a,b,cin,sum,co);
/*INSTANTIATE THE MODULE NAME(adder8bit_task4bit) THAT NEEDS BE TESTED WITH INSTANTIATION NAME add_task*/
initial
begin
cin=0;
repeat(10)
begin
#5 a=$random; b=$random;
end
end
initial
#150 $finish;
initial
$monitor($time, "a=%b, b=%b, sum=%b, co=%b)" , a, b, sum, co);
endmodule
input [7:0]a,b;
input cin;
output reg [7:0]sum;
output reg co;
reg cint;
task task4bit;
input [3:0]a_task, b_task;
input cin_task;
output [3:0]sum_task;
output co_task;
{co_task,sum_task}=a_task + b_task + cin_task;
endtask
always@(*)
begin
task4bit(a[3:0], b[3:0], cin, sum[3:0], cint);
task4bit(a[7:4], b[7:4], cint, sum[7:4], co);
end
endmodule
Test bench
`timescale 1ns/1ps
module test_adder8bit;
reg [7:0]a,b;
reg cin;
wire [7:0]sum;
wire co;
adder8bit_task4bit add_task(a,b,cin,sum,co);
/*INSTANTIATE THE MODULE NAME(adder8bit_task4bit) THAT NEEDS BE TESTED WITH INSTANTIATION NAME add_task*/
initial
begin
cin=0;
repeat(10)
begin
#5 a=$random; b=$random;
end
end
initial
#150 $finish;
initial
$monitor($time, "a=%b, b=%b, sum=%b, co=%b)" , a, b, sum, co);
endmodule
Answered by
1
module adder8bit_task4bit(a,b,cin,sum,co);
input [7:0]a,b;
input cin;
output reg [7:0]sum;
output reg co;
reg cint;
task task4bit;
input [3:0]a_task, b_task;
input cin_task;
output [3:0]sum_task;
output co_task;
{co_task,sum_task}=a_task + b_task + cin_task;
endtask
always@(*)
begin
task4bit(a[3:0], b[3:0], cin, sum[3:0], cint);
task4bit(a[7:4], b[7:4], cint, sum[7:4], co);
end
endmodule
Test bench
`timescale 1ns/1ps
module test_adder8bit;
reg [7:0]a,b;
reg cin;
wire [7:0]sum;
wire co;
adder8bit_task4bit add_task(a,b,cin,sum,co);
/*INSTANTIATE THE MODULE NAME(adder8bit_task4bit) THAT NEEDS BE TESTED WITH INSTANTIATION NAME add_task*/
initial
begin
cin=0;
repeat(10)
begin
#5 a=$random; b=$random;
end
end
initial
#150 $finish;
initial
$monitor($time, "a=%b, b=%b, sum=%b, co=%b)" , a, b, sum, co);
endmodule
input [7:0]a,b;
input cin;
output reg [7:0]sum;
output reg co;
reg cint;
task task4bit;
input [3:0]a_task, b_task;
input cin_task;
output [3:0]sum_task;
output co_task;
{co_task,sum_task}=a_task + b_task + cin_task;
endtask
always@(*)
begin
task4bit(a[3:0], b[3:0], cin, sum[3:0], cint);
task4bit(a[7:4], b[7:4], cint, sum[7:4], co);
end
endmodule
Test bench
`timescale 1ns/1ps
module test_adder8bit;
reg [7:0]a,b;
reg cin;
wire [7:0]sum;
wire co;
adder8bit_task4bit add_task(a,b,cin,sum,co);
/*INSTANTIATE THE MODULE NAME(adder8bit_task4bit) THAT NEEDS BE TESTED WITH INSTANTIATION NAME add_task*/
initial
begin
cin=0;
repeat(10)
begin
#5 a=$random; b=$random;
end
end
initial
#150 $finish;
initial
$monitor($time, "a=%b, b=%b, sum=%b, co=%b)" , a, b, sum, co);
endmodule
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