A 4-bit carry lookahead adder, which adds two 4-
bit numbers, is designed using AND, OR, NOT,
NAND, NOR gates only. Assuming that all the
inputs are available in both complemented and
uncomplemented forms and the delay of each
gate is one time unit, what is the overall
propagation delay of the adder? Assume that
the carry network has been implemented using
two-level AND-OR logic.
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sorry but I can't know
but t tried
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