Question

A Direct mapped cache has a capacity of 16-word cache and a block size of 1 word . Consider the following repeating sequence of 1w addresses (given in hexadecimal ):
74 A0 78 38C AC 84 88 8C 7C 34 38 13C 388 18C
Determine the effective miss rate if the sequence is input to the following caches ,ignoring startup effects.

Answer 1

Here is a series of addresses in hexadecimal:

20(w), 3C(r), 10(r), 16(w), 20(r), 04(w), 28(r), 6(r), 10(w), 17(w)

Assume a LRU replacement algorithm. Draw each of the following caches as it would appear at the end of the series of references, including valid bit, dirty bit and tag:

a. A direct-mapped cache with block size of 16 words

b. 2-way set-associative cache with block size of 8 words

c. 4-way set-associative cache with block size of 4 words

d. A fully associative cache with block size of 32 words

Show the contents of the memory block using the byte address range such as M[20-23] for