Question

A five-stage pipelined processor has IF, ID, EXE, MEM, WB. The IF, ID, WB stages takes 1 clock
cycles each for any instruction. The execution of different instructions takes more than ideal time as
given:- 2 clock cycle for an ADD instruction, 1 clock cycles for SUB instruction, 2 clock cycles for
MUL instructions, 2 clock cycles for DIV instructions, 1 clock cycles for LOAD and 2 clock cycle for
STORE instructions respectively.
Consider the following instructions:-
ADD R2, R3, R6
LOAD R3, (25)R5
SOTRE (10)R6, R3
DIV R7, (10)R6, R3
SUB R1, R7, R5
STORE (04)R8, R1
MUL R4, R7, (04)R8
For the above sequence of instructions draw time and space diagram in order to find out a total number
of clock cycles required to complete their execution without using operand forwarding?

Answer 1

Answer:

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Answer 2

Answer:

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