Question

A hypothetical machine has 64 general purpose registers of 64 bits each. The machine has 4G word of RAM (assume that each word is of 64 bits and memory is word addressable). The instructions of machine are of fixed format and are 64 bit long. Instructions of the machine consist of operation code, addressing mode specification, one register operand and one memory operand. The machine uses 2 bits to specify addressing mode as given below: Addressing mode bits Register operand Memory operand 00 Direct Direct 01 Direct Immediate data 10 Register Indirect Direct 11 Register indirect immediate data Machine can specify 1024 different operation codes. Assume that the machine has named 5 of its general purpose registers based on their possible role in instruction execution as Program Counter (PC), Accumulator (AC), Memory Address Register (MAR), Instruction Register (IR) , Data Register (DR) and Flag registers (FR). Perform the following tasks for the machine. (i) Specify the size of different fields that are needed in the instruction. (You may leave some bits as unused). (ii) Put some valid values in certain registers and memory locations and demonstrate examples of different addressing modes of this machine. (iii) Assuming that the instructions are first fetched to Instruction Register (IR) and the two operands are transferred to AC and DR registers respectively, and result of operation is stored in the AC register; write and explain the sequence of microoperations that are required for fetch and execute cycles of an ADD instruction having addressing mode bits as 01. Make and state suitable assumptions, if any

Answer 1

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