Question

A pulse train can be delayed by a finite nimber of periods using clock in

Answer 1

Hey,
Thanks for answering this question.


A pulse train can be delayed by a finite number of periods by using clock in a SERIAL IN-SERIAL OUT SHIFT REGISTER.

This is so because by using shift register, using D-flip flop, we can delay serial input signal to appear at serial output by keeping clock at low level for some finite amount of time.


Hope this answer helps.