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Lock synchronization overheads may be significant in a shared-memory multiprocessor systemon-a-chip (SoC) implementation. These overheads are observed in terms of lock latency, lock delay and memory bandwidth consumption in the system. There has been much previous work to speedup access of lock variables via specialized caches, software queues and delayed loops, e.g., exponential back off . However, in the context of SoC, these previously reported techniques all have drawbacks not present in our technique. We present a novel, efficient, small and very simple hardware unit, SoC Lock Cache (SoCLC), which resolves the critical section (CS) interactions among multiple processors and improves the performance criteria in terms of lock latency, lock delay and bandwidth consumption in a shared-memory multiprocessor SoC. Our mechanism is capable of handling short CSs as well as long CSs.
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