Computer Science, asked by kakarsalil4469, 11 months ago

assume an instruction cache miss rate for gcc of 3% and a data cache miss rate of 5%. If a machine has a cpi of 4 without any memory stalls and the miss penalty is 30 cycles for all misses,determine how much faster a machine would run with a perfect cache that never missed. Assume 40% of instructions are loads/stores."

Answers

Answered by Anonymous
70

of 3% and a data cache miss rate of 5%. If a machine has a cpi of 4 without any memory stalls and the miss penalty is 30 cycles for all misses,determine how much faster a machine would run with a perfect cache that never missed. Assume 40% of instructions are loads/stores."

Answered by sameeksha712rawat
0

Answer:

A machine would run 1.375 times faster with a perfect cache that never missed.

Explanation:

Monitoring and Analysis of Cache Performance

The CPU time is divided into two parts:

  1. Memory-stall clock cycles
  2. CPU execution clock cycles

CPU time = (CPU execution clock cycles + Memory-stall clock cycles) x Clock cycle time

  • Memory-stall clock cycles = Read-stall cycles + Write-stall cycles
  • Read-stall cycles = Reads/Program x Read miss rate x Read miss penalty
  • Write-stall cycles = (Writes/Program x Write miss rate x Write miss penalty) + Write buffer stall
  • Read and Write stall cycles can be combined by using single miss rate and miss penalty

Memory-stall clock cycles = Memory accesses/Program x Miss rate x Miss penalty

It is also possible to write it as:

Memory-stall clock cycles = Instructions/Program x Miss/Instruction x Miss penalty

Lets solve the above question,

as given,

  • instruction miss rate = 3%
  • data miss rate = 5%
  • CPI = 4 (without any memory stalls)
  • miss penalty = 30 cycles
  • instructions loads/stores = 40%

Instruction miss cycle = I x 3% x 30 = 0.90 I (since, I = instructions)

Data miss cycles = I x 40% x 5% x30 = 0.6 I

Total memory stall cycles = 0.90 I + 0.6 I = 1.5 I

CPIstall = 4 + 1.5 = 5.5

CPU time with stalls/CPU time with perfect cache = I x CPIstall x Clock cycle/I x CPIperfect x Clock cycle = 5.5 / 4 = 1.375

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