Math, asked by shivamnmishra153, 23 days ago

Assume that main memory accesses take 70 ns and that memory

accesses are 36% of all instructions. The following table shows

data for L1 caches attached to each of two processors, P1 and P2.

P1 P2

L1 Size 2 KiB 4 KiB

L1 Miss Rate 8.0% 6.0%

L1 Hit Time 0.66 ns 0.90 ns​

Answers

Answered by smrutitanayapradhan
1

Answer:

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