Assume we have 2 multipliers, 2 adders, 1 divide & 1 integer unit. The following set of MIPS
instruction is going to be executed in a pipelined system.
Consider the following instructions:-
MUL R3, R5, R4
ADD R7, R3, R5
SUB R6, R7, R5
LOAD R6, 48(F5)
LOAD R9, 48(F5)
MUL R10, R9, R3
DIV R7, R3, R2
ADD R2, R7, R3
Consider the following execution status for the above instruction set:-
1
st MUL instruction is completed in its write result phase.
All other remaining instruction is in its execution phase.
Show the status of instruction, reservation station, & register result status using dynamic scheduling
with the Scoreboard approach.
Answers
Consider the following instructions :- STORE 20(R1), R6 SUB R2, R3, R4 DIV R2, R2, R5 LOAD R2, 11(R6) ADD R7, R2, R4 LOAD R9, 9(R8) BEQZ R9, L2 MUL R9, R7, R2 LOAD R11, (0)R7 ADD R9, R11, R3 MUL R8, R2,R11 END L2:- DIV R7, R1,R8 ADD R6, R7, R8 If the branch instruction is not taken in the above sequence of instructions, then find out the total number of clock cycles required to complete their execution by using operand forwarding. 12.Consider the following instructions:- SUB R1, R3, R2 LOAD R2, 10(R5) STORE (04)R8, R2 DIV R3, R2, R1 SUB R2, R3, R1 BNEQZ R2, L1 LOAD R7, 14(R6) ADD R8, R7, R2 DIV R9, R8, R7 END L1:- LOAD R7, 11(R2) SUB R4, R7,R5 MUL R7, R4, R5 If the branch instruction is taken in the above sequence of instructions, then find out the independent instruction which can be enter in to delayed slot for all possible cases in order to improve the system