Question

Clocked flip flop experiment​

Answer 1

Explanation :-

RS flip-flop is an asynchronous sequential logic circuit(Circuit-1 of M14). By adding a gate to the input of basic circuit, it can be made that the flip-flop can response within one clock pulse(CP) occurrence period. ... The clock part RS flip-flop becomes Q=1 when S=1, R=0 and CP=1, and this status is called set status.