comparison of LFSR with RO-PUF
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Nowadays Field-Programmable Gate Arrays (FPGAs) are widely used for consumer electronics, automotives, aerospace equipment and other various industrial products. Considering the fact that FPGAs are widespread among the vital and security-critical modules, protecting the confiden- tiality and integrity of FPGA bitstreams is of significant con- cern for both users and manufacturers. Since the bitstream is simply an electronic stream downloaded when the device is configured, it is always threatened by piracy such as illegal cloning and cracking.
For the security purpose, some of the recent FPGAs have an AES or Triple DES core to support encrypted bitstreams, and some of the latest FPGAs also have an HMAC core to enable bitstream authentication. However, the secret key of the encryption core embedded in the FPGA can be revealed by the state-of-the-art attack called side-channel attack [1],
[2], which statistically analyzes the power consumption or electromagnetic emanation of the devices. Recently the bit- stream security mechanisms of some FPGAs are reportedly
broken by side-channel attacks [3], [4].
Considering the above situation, Physical Unclonable Functions (PUFs) [5] can be the solution to the security issues of FPGAs. A PUF is an object that outputs a device- specific response by extracting its intrinsic physical charac- teristics. A silicon PUF (hereafter simply “PUF”) is a circuit constructed on semiconductor and outputs a unique ID by exploiting variation of gate length, threshold voltage, non- uniform density of impurity and so on. By using a PUF for key generation, the secret key need not be fixed in the FPGA, and therefore, the PUF can protect the device against side-channel attacks. Another novelty of using the PUF for FPGAs is that different IDs can be generated from the same bitstream. The bitstreams are common for all devices but the device-specific data are generated from the device variation. Note that the bitstream itself need not include any secret information. As a consequent, the bitstream of the PUF can be transferred over non-secure network channels.
Maes and Verbauwhede categorized PUFs into non- electronic PUFs, analog electronics PUFs, delay-based in- trinsic PUFs and memory-based intrinsic PUFs [6]. Among these PUFs, the delay-based and memory-based ones can be applied to FPGAs. The examples of the delay-based PUFs are arbiter PUF [7], ring oscillator (RO) PUF [8], Glitch PUF [9], etc., and the examples of the memory-based PUFs include SRAM PUF [10], butterfly PUF [11], tri-state PUF [12], etc.
However, these PUFs have some shortcomings. The delay- based PUFs usually output only one- or several-bit response at once and consequently have low throughput. Memory- based PUFs output multiple bits in parallel but the output values are fixed; addressable memory-based PUFs are pos- sible to output variable IDs but the circuit size becomes considerably large.
To eliminate these shortcomings, we developed a PUF with the new structure called Pseudo-LFSR PUF (PL-PUF). The structure of the PL-PUF is based on the Liner Feedback Shift Register (LFSR) but it actually does not consist of shift register; it composes large combinational logic. The PL- PUF efficiently outputs a long-bit and variable ID, and the size of the PL-PUF circuit is reasonably small. Furthermore, the challenge-response mapping of the PL-PUF is variable depending the active duration of the circuit, that is, a single PL-PUF behaves as if it has multiple different PUF cores.
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For the security purpose, some of the recent FPGAs have an AES or Triple DES core to support encrypted bitstreams, and some of the latest FPGAs also have an HMAC core to enable bitstream authentication. However, the secret key of the encryption core embedded in the FPGA can be revealed by the state-of-the-art attack called side-channel attack [1],
[2], which statistically analyzes the power consumption or electromagnetic emanation of the devices. Recently the bit- stream security mechanisms of some FPGAs are reportedly
broken by side-channel attacks [3], [4].
Considering the above situation, Physical Unclonable Functions (PUFs) [5] can be the solution to the security issues of FPGAs. A PUF is an object that outputs a device- specific response by extracting its intrinsic physical charac- teristics. A silicon PUF (hereafter simply “PUF”) is a circuit constructed on semiconductor and outputs a unique ID by exploiting variation of gate length, threshold voltage, non- uniform density of impurity and so on. By using a PUF for key generation, the secret key need not be fixed in the FPGA, and therefore, the PUF can protect the device against side-channel attacks. Another novelty of using the PUF for FPGAs is that different IDs can be generated from the same bitstream. The bitstreams are common for all devices but the device-specific data are generated from the device variation. Note that the bitstream itself need not include any secret information. As a consequent, the bitstream of the PUF can be transferred over non-secure network channels.
Maes and Verbauwhede categorized PUFs into non- electronic PUFs, analog electronics PUFs, delay-based in- trinsic PUFs and memory-based intrinsic PUFs [6]. Among these PUFs, the delay-based and memory-based ones can be applied to FPGAs. The examples of the delay-based PUFs are arbiter PUF [7], ring oscillator (RO) PUF [8], Glitch PUF [9], etc., and the examples of the memory-based PUFs include SRAM PUF [10], butterfly PUF [11], tri-state PUF [12], etc.
However, these PUFs have some shortcomings. The delay- based PUFs usually output only one- or several-bit response at once and consequently have low throughput. Memory- based PUFs output multiple bits in parallel but the output values are fixed; addressable memory-based PUFs are pos- sible to output variable IDs but the circuit size becomes considerably large.
To eliminate these shortcomings, we developed a PUF with the new structure called Pseudo-LFSR PUF (PL-PUF). The structure of the PL-PUF is based on the Liner Feedback Shift Register (LFSR) but it actually does not consist of shift register; it composes large combinational logic. The PL- PUF efficiently outputs a long-bit and variable ID, and the size of the PL-PUF circuit is reasonably small. Furthermore, the challenge-response mapping of the PL-PUF is variable depending the active duration of the circuit, that is, a single PL-PUF behaves as if it has multiple different PUF cores.
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