Question

Computer Science
Write the fetch and execute cycles Control steps of the following instructions and calculate the clock
cycles needed in the execution cycle for each of these instructions
Ili need number of clock cycle
1-ADD (R1), R2
2- .MOV R1, (R2)
3-Jump Label_A
4-ADD R2, R1
plz i want corerct answer 100%...​

Answer 1

ANSWER

Consider an instruction pipeline with four stages with the stage delays 5

nsec, 6 nsec, 11 nsec, and 8 nsec respectively. The delay of an inter-stage

register stage of the pipeline is 1 nsec. What is the approximate speedup of

the pipeline in the steady state under ideal conditions as compared to the

corresponding non-pipelined implementation?

a. 4.0

b. 2.5

c. 1.1

d. 3.0

Correct answer is (b).

Time taken to execute N instructions in non-pipelined implementation will

be (5 + 6 +