Question

Consider a paged logical address space (composed of 32 pages of 2 k bytes each) mapped into a 1-mbyte physical memory space.

a. what is the format of the processor's logical address?

b. what is the length and width of the page table (disregarding the "access rights" bits)?

c. what is the effect on the page table if the physical memory space is reduced by half?

Answer 1

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