Question

Consider a RISC-V implementation with full-forwarding and a hazard detection unit. Assuming that the
branch outcome is known in the MEM stage, what are the values of PCWrite, IF/IDWrite, ForwardA, and
ForwardB signals at each clock cycle during the execution of the following program? How many clock cycles
are needed for executing this entire program?
LW xl, 20 (x2)
ADD x2, x1, x1
SUB x1, x1, x2
BEQ x1, x2, Exit​

Answer 1

Answer:

Consider a RISC-V implementation with full form

Explanation:

LW xl ,20(X2)

ADD x2 ,X1,x3

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