Question

Consider the following Verilog HDL code:
always @ (posedge Clock or posedge Clear or posedge Set)
begin
If (Set = 1'bl) begin
Q<= l'bl; end
else if (Clear = l'bl) begin
Q<= 1'b0; end
else begin
Q<= M; end //Here M is the only one input of the flip-flop
end
What flipflop does the Verilog code analogues? What is the flip flop output if Clear =
l' and Set = '1'?
(a) Synchronous D flip flop, Q = 0
(b) Asynchronous T flip flop. Q = 0
(c) Asynchronous D flip flop, Q = 1
(d) Synchronous T flip flop, Q = 1
​

Answer 1

Explanation:

Ans is synchtonous D flipflop Q=0