Consider the PLL shown in Figure Q2. Assume that: i) the phase detector is a simple CMOS EXOR whose logic levels are ground and VDD = 5V, ii) both the input to the loop and the VCO output are square waves that swing between ground and VDD, and iii) the VCO has a perfectly linear relationship between the control voltage and output frequency of 10 MHz/V. The polarities are such that an increase in control voltage causes an increase in the VCO frequency
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