Describe simd architecture and programming principles
Answers
✔SIMD Architecture (Single instruction Multiple Data)
⭐Single instruction is applied to a multiple data item to produce the same output.
⭐Master instruction work on vector of operand
⭐No of processors running the same instruction one clock cycle by the strict lock approach
⭐It is type of Instruction level parallelism
⭐Communication network allow parallel synchronous communication between several Processing Element / Memory modules.
✔Programming Principle :
CU to PEs communication:
The data is distributed from CU to PEs., one invloves distribution of data to all PEs and the other one is between PE and the CU.
Instruction, BROADCAST, R - Broadcast the data to all processing elements where all PEs receive and stores the data in the register R. Data is in the D register of CU
Routing instruction are used such as WRAPTB- wrap end around connection top bottom , WRAPLR- wrap end around connection left right, UNWRAPTB-Unwrap top bottom, UNWRAPLR- unwrap left right
PE computing
There are numerous instructions available for computing the processing element.
Instruction like PFADD R1,R2- Parallel float addition , PFSUB- parallel float subtraction etc
PE port to PE GPRS instructions - PMOV R,LP- parallel move in to register R from the right port , PMOV R,TP- Parallel move in to register R from the top port
PE GPRS to PE Port instructions:
PMOV RP,R- Parallel move in to right port from register R etc
Instructions for PEs to PEs:- PIN Lp- parallel the data to left port, PIN RP- right port etc
Example Mesh connected architecture
ILLIAC-IV
The ILLIAC-IV project was started in 1966 at the University of Illinois.
A system with 256 processors controlled by a CP was envisioned.
The set of processors was divided into four quadrants of 64 processors.
⭐Single instruction is applied to a multiple data item to produce the same output.
⭐Master instruction work on vector of operand
⭐No of processors running the same instruction one clock cycle by the strict lock approach
⭐It is type of Instruction level parallelism