Question

Design a circuit for even parity generator and checker for 3-bit message

Answer 1

Let us know the even parity bit is transmitted with 3-bit messages. And the three inputs like A, B and C for output with parity bit P to apply for the circuits. Firstly the even parity bit P must have a total number of bits.

In the input screen, the odd numbers must be present with even parity 'P' and must be '1'. Therefore the result has to contain the combination of input 'p' must be '0.'

P=W′X′Y+W′XY′+WX′Y′+WXY

P=W′(X′Y+XY′)+W(X′Y′+XY)

P=W′(X⊕Y)+W(X⊕Y)′=W⊕X⊕Y