Question

Design a recognizer that recognizes an input sequence that has at least three 1's. The recognizer has a single input x, and a single output y, in addition to an asynchronous reset signal. The recognizer sets the output y to 1 if the input signal x was equal to 1 in at least 3 clock cycles after the reset was asserted. For the above recognizer described above:

Answer 1

Answer:

hi hi hi hi hi hi hi hi hi hi hi hi hi hi hi hi hi