Design a synchronous counter with T-flipflops that has a mode control with following specifications. When Mode = 0, the circuit works as a mod-3 up counter, and when Mode = 1, the circuit works as a mod-5 up counter. *
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Answer:
D-type Flip-flops
MOD counters are made using “flip-flops” and a single flip-flop can produce a count of 0 or 1, giving a maximum count of 2. There are different types of flip-flop designs we could use, the S-R, the J-K, J-K Master-slave, the D-type or even the T-type flip-flop to construct a counter. But to keep things simple, we will use the D-type flip-flop, (DFF) also known as a Data Latch, because a single data input and external clock signal are used, and is also positive edge triggered.
The D-type flip-flop, such as the TTL 74LS74, can be made from either S-R or J-K based edge-triggered flip-flops depending on whether you want it to change state either on the positive or leading edge (0 to 1 transition) or on the negative or trailing edge (1 to 0 transition) of the clock pulse. Here we will assume a positive, leading-edge triggered flip-flop. You can find more information in the following link about D-type flip-flops.
D-type Flip-flop and Truth Table
d type flip flop
The operation of a D-type flip-flop, (DFF) is very simple as it only has a single data input, called “D”, and an additional clock “CLK” input. This allows a single data bit (0 or 1) to be stored under the control of the clock signal thus making the D-type flip-flop a synchronous device because the data on the inputs is transferred to the flip-flops output only on the triggering edge of the clock pulse.
So from the truth table, if there is a logic “1” (HIGH) on the Data input when a positive clock pulse is applied, the flip-flop SET’s and stores a logic “1” at “Q”, and a complimentary “0” at Q. Likewise, if there is a LOW on the Data input when another positive clock pulse is applied, the flip-flop RESET’s and stores a “0” at “Q”, and a resulting “1” at Q.
Then the output “Q” of the D-type flip-flop responds to the value of the input “D” when the clock (CLK) input is HIGH. When the clock input is LOW, the condition at “Q”, either “1” or “0” is held until the next time the clock signal goes HIGH to logic level “1”. Therefore the output at “Q” only changes state when the clock input changes from a “0” (LOW) value to a “1” (HIGH) making it a positive edge triggered D-type flip-flop. Note that negative edge-triggered flip-flops work in exactly the same way except that the falling edge of the clock pulse is the triggering edge.
So now we know how an edge-triggered D-type flip-flop works, lets look at connecting some together to form a MOD counter.