Difference between pipelined and non-pipelined microprocessor bus cycle
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Pipelined microprocessor bus cycle is an implementation technique where multiple instructions are overlapped in execution and has high throughput (amount of instructions executed per unit time).
The pipeline is filled by the CPU scheduler from a pool from a piece of work which is waiting to occur and each execution unit has a pipeline attache to it so as to have work pre planned.
The efficiency of pipeline microprocessor bus depends on the effectiveness of the CPU scheduler.
If the work load is such that the scheduler can't do a good job, frequent pipeline stalls occur.
Non- pipeline microprocessor bus cycle is all the actions, (decoding, encoding, executing of instructions, and writing the results on the memory) are grouped in to a single step.
It has a low throughput.
The CPU scheduler in the case of non pipeline merely chooses from the pool of waiting work when the execution unit gives a single that is free.
It is not dependent on the scheduler.
The pipeline is filled by the CPU scheduler from a pool from a piece of work which is waiting to occur and each execution unit has a pipeline attache to it so as to have work pre planned.
The efficiency of pipeline microprocessor bus depends on the effectiveness of the CPU scheduler.
If the work load is such that the scheduler can't do a good job, frequent pipeline stalls occur.
Non- pipeline microprocessor bus cycle is all the actions, (decoding, encoding, executing of instructions, and writing the results on the memory) are grouped in to a single step.
It has a low throughput.
The CPU scheduler in the case of non pipeline merely chooses from the pool of waiting work when the execution unit gives a single that is free.
It is not dependent on the scheduler.
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