Question

Difference between simulation and synthesis in vhdl

Answer 1

Simulator uses the sensitivity list to figure out when it needs to run the process. ... Simulation is used to verify the functionality of the circuit. Synthesis is used for converting VHDL description into a set of primitives (equations as in CPLD) or components (as in FPGA's) to fit into the target technology.

Answer 2

Answer:

द एंगल बिटवीन द रिफ्लेक्टिव एंड नॉरमल इस कॉल्ड एंगल ऑफ रिफ्लेक्शन एंड द क्लांस ऑफ एंगल ऑफ रिफ्लेक्शन बाय द लॉर्ड ऑफ इंसिडेंट