Physics, asked by ristandur4462, 1 year ago

Explain and draw CMP architectures.

Answers

Answered by thoshithgowda17

Answer:

If a thread can not use all the computing resources of the CPU (because instructions depend on each other's result), running another thread permits to not leave these idle. If several threads work on the same set of data, they can actually share its caching, leading to better cache usage or synchronization on its values.

If a thread gets a lot of cache misses, the other thread(s) can continue, taking advantage of the unused computing resources, which thus can lead to faster overall execution, as these resources would have been idle if only a single thread was executed

3. What are the two levels of thread?

Ø User Threads

Ø Kernel Threads

4. What are the multithreading models available?

Ø Many threads on one LWP (many-to-one)

Ø One thread per LWP (one-to-one)

Ø Many threads on many LWPs (many-to-many)

5. What is Many-to-one model?

The many-to-one model maps many user-level threads to one kernel thread. Advantages: Totally portable More efficient Disadvantages: cannot take advantage of parallelism The entire process is block if a thread makes a blocking system call Mainly used in language systems, portable libraries like solaris 2

6. What is One-to-one model?

The one-to-one model maps each user thread to a kernel thread. Advantages: allows parallelism Provide more concurrency Disadvantages: Each user thread requires corresponding kernel thread limiting the number of total threads Used in LinuxThreads and other systems like Windows 2000,Windows NT

7. What is Many-to-many model?

The many-to-many model multiplexes many user-level threads to a smaller or equal number of kernel threads. Advantages: Can create as many user thread as necessary Allows parallelism Disadvantages: kernel thread can the burden the performance Used in the Solaris implementation of Pthreads (and several other Unix implementations)

8. What are the factors will affect issue slot?

Imbalances in the resource needs.

Ø Resource availability over multiple threads.

Ø Number of active threads considered.

Ø Finite limitations of buffer.

Ø Ability to fetch enough instructions from multiple threads.

Ø Practical limitations of what instructions combinations can issue from one thread and multiple threads.

9. Give Comparison of SMT vs Superscalar

SMT processors are compared to base superscalar processors in several key measures:

Ø Utilization of functional units.

Ø Utilization of fetch units.

Ø Accuracy of branch predictor.

Ø Hit rates of primary caches.

Ø Hit rates of secondary caches.

10. Draw the architecture of Single core computer

11. What are the design issues of SMT & CMP architectures?

They determine the performance measures of each processor in a precise manner. The issue slots usage limitations and its issues also determine the performance.Why Multithreading Today ILP is exhausted, TLP is in. Large performance gap between MEMORY and PROCESSOR. Too many transistors on chip. More existing MT applications today. Multiprocessors on a single chip. Long network latency, too

12. What is a Multi-core processor?

Each core has its execution pipeline. No limitation for the number of cores that can be placed in a single chip. Two cores run at slower speeds and lower temperatures. But the combined throughput > single processor. The fundamental relationship b/w freq. and power can be used to multiply the no. of cores from 2 to 4, 8 and even higher

13. What are the benefits of Intel Multi-core processor?

Ø Multi-core performance.

Ø Dynamic scalability.

Ø Design and performance scalability

Ø Intelligent performance on-demand

Ø Increased performance on Highly-threaded apps.

Ø Scalable shared memory.

14. What is a IBM cell processor?

A chip with one PPC hyper-threaded core called PPE and eight specialized cores called SPEs.The challenge to be solved by the Cell was to put all those cores together on a single chip. This was made possible by the use of a bus with outstanding performance

The Cell processor can be split into four components:

Ø external input and output structures,

Ø the main processor called the Power Processing Element (PPE)

Ø eight fully-functional co-processors called the Synergistic Processing Elements, or SPEs,

Ø a specialized high-bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB.

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