Question

explain Block diagram of DMA​

Answer 1

A device controller need not necessarily control a single device. It can usually control multiple I/O devices. It comes in the form of an electronic circuit board that plugs directly into the system bus, and there is a cable from the controller to each device it controls. The cables coming out of the controller are usually terminated at the back panel of the main computer box in the form of connectors known as ports.

The Figure 2 below illustrates how I/O devices are connected to a computer system through device controllers. Please note the following points in the diagram:

 

• Each I/O device is linked through a hardware interface called I/O Port.

• Single and Multi-port device controls single or multi-devices.

• The communication between I/O controller and Memory is through bus only in case of Direct Memory Access (DMA), whereas the path passes through the CPU for such communication in case of non-DMA.

 

Using device controllers for connecting I/O devices to a computer system instead of connecting them directly to the system bus has the following advantages:

• A device controller can be shared among multiple I/O devices allowing many I/O devices to be connected to the system.

• I/O devices can be easily upgraded or changed without any change in the computer system.

• I/O devices of manufacturers other than the computer manufacturer can be easily plugged in to the computer system. This provides more flexibility to the users in buying I/O devices of their choice.


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Answer 2

The data transfer technique in which peripherals manage the memory buses for direct interaction with main memory without involving the CPU is called direct memory access (DMA). Using DMA technique large amounts of data can be transferred between memory and the peripheral without severely impacting CPU performance.

During the DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller takes over the buses to manage the transfer directly between the I/O device(s) and main memory. The structure of DMA controller is described below.

Figure: Block Diagram of DMA Controller

The control unit communicates the CPU via data bus and control lines.

The DMA controls/relinquishes the system bus using BR (Bus Request) and BG (Bus Grant) signals. DMA operates read and write operations via RD (Read) and WR (Write) signals. DMA sends request and acknowledge to I/O devices via DMA request and DMA acknowledge signals.

The registers in DMA are selected by CPU through the address bus by enabling DS (DMA Select) and RS (Register Select) inputs.

All registers in the DMA appear to the CPU as I/O interface registers. The address register contains an address to specify the desired location in memory. It is incremented after each word that is transferred to the memory. The word count register holds the number of words to be transferred. It is decremented by one after each word transfer and internally tested for zero. The control register specifies the mode of transfer.

The DMA transfer operation is described below:

Figure: Direct Memory Access Technique

The DMA request CPU to handle control of buses to the DMA using bus request (BR) signal. The CPU grants the control of buses to DMA using bus grant (BG) signal after placing the address bus, data bus and read and write lines into high impedance state (which behave like open circuit).

CPU initializes the DMA by sending following information through the data bus.

Starting address of memory block for read or write operation.

The word count which is the no. of words in the memory block.

Control to specify the mode of transfer such as read or write.

A control to start the DMA transfer.

The DMA takes control over the buses directly interacts with memory and I/O units and transfers the data without CPU intervention. When the transfer completes, DMA disables the BR line. Thus CPU disable BG line, takes control over the buses and return to its normal operation.

The DMA transfer operation is illustrated below:

Fig: Illustration for DMA transfer in a computer system

DMA Transfer Modes

There are 3 different modes of DMA data transfer. They vary by how DMA controller determines when to transfer data (but actual data transfer process remains the same in all three cases).

(a) Burst Mode

Entire block of data is transferred in one continuous sequence.

Once the DMA controller is granted access to the system bus by CPU, it transfer all bytes of data in the data block before relinquishing control of system buses back to the CPU.

This mode is useful for loading programs or data files into memory, but it keeps CPU idle for relatively long period of time.

(b) Cycle Stealing Mode

DMA controller obtains access to system bus as in burst mode; transfers one byte of data and returns the control of the system bus to CPU. It continually issues requests using Bus Request (BR) signals, transferring one byte of data per request, until it has transferred its entire block of data. (steals one CPU cycle).

The data block is not transferred as quickly as in burst mode, but the CPU is not idled for long period of time as in burst mode.

(c) Transparent Mode

DMA controller only transfers data when CPU is performing operations that do not use system buses.

The main advantage of this mode is that CPU never stops executing its program.

The main disadvantages of this mode are

Hardware needed to determine when the CPU is not using the system buses can be quite complex and relatively expensive.

Requires highest time to transfer a block of data as compared to above two modes.