Question

Explain in detail RISC pipeline. Why is the cache miss penalty greater in deeply pipelined processor?

Answer 1

Answer:

A full cache miss must (at least) load an entire cache line from DRAM. ... When uA2 takes a cache miss, it stalls for 100 ns, e.g. 100 clock cycles, e.g. 100 issue slots. Here the cache miss penalty (expressed in instruction issue slots missed), is twice as large in the more deeply pipelined processor.

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