features of pentium processor
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Features of Pentium Processor are as follows:
64 bit data bus
8 bytes of data information can be transferred to and from memory in a single bus cycle
Supports burst read and burst write back cycles
Supports pipelining
Instruction cache
8 KB of dedicated instruction cache
Two Integer execution units, one Floating point execution unit
Dual instruction pipeline
256 lines between instruction cache and prefetch buffers; allows 32 bytes to be transferred from cache to buffer
Data cache
8 KB dedicate data cache gives data to execution units
32 byte lines
Two parallel integer execution units
Allows the execution of two instructions to be executed simultaneously in a single processor clock
Floating point unit
It includes
Faster internal operations
Local advanced programmable interrupt controller
Speeds up upto 5 times for common operations including add, multiply and load, than 80486
Branch Prediction Logic
To reduce the time required for a branch caused by internal delays
When a branch instruction is encountered, microprocessor begins prefetch instruction at the branch address
Data Integrity and Error Detection
Has significant error detection and data integrity capability
Data parity checking is done on byte – byte basis
Address parity checking and internal parity checking features are added
Dual Integer Processor
Allows execution of two instructions per clock cycle
Functional redundancy check
To provide maximum error detection of the processor and interface to the processor
A second processor ‘checker’ is used to execute in lock step with the ‘master’ processor
It checks the master’s output and compares the value with the internal computed values
An error signal is generated in case of mismatch
Superscalar architecture
Three execution units
One execution unit executes floating point instructions
The other two (U pipe and V pipe) execute integer instructions
Parallel execution of several instructions – superscalar processor
64 bit data bus
8 bytes of data information can be transferred to and from memory in a single bus cycle
Supports burst read and burst write back cycles
Supports pipelining
Instruction cache
8 KB of dedicated instruction cache
Two Integer execution units, one Floating point execution unit
Dual instruction pipeline
256 lines between instruction cache and prefetch buffers; allows 32 bytes to be transferred from cache to buffer
Data cache
8 KB dedicate data cache gives data to execution units
32 byte lines
Two parallel integer execution units
Allows the execution of two instructions to be executed simultaneously in a single processor clock
Floating point unit
It includes
Faster internal operations
Local advanced programmable interrupt controller
Speeds up upto 5 times for common operations including add, multiply and load, than 80486
Branch Prediction Logic
To reduce the time required for a branch caused by internal delays
When a branch instruction is encountered, microprocessor begins prefetch instruction at the branch address
Data Integrity and Error Detection
Has significant error detection and data integrity capability
Data parity checking is done on byte – byte basis
Address parity checking and internal parity checking features are added
Dual Integer Processor
Allows execution of two instructions per clock cycle
Functional redundancy check
To provide maximum error detection of the processor and interface to the processor
A second processor ‘checker’ is used to execute in lock step with the ‘master’ processor
It checks the master’s output and compares the value with the internal computed values
An error signal is generated in case of mismatch
Superscalar architecture
Three execution units
One execution unit executes floating point instructions
The other two (U pipe and V pipe) execute integer instructions
Parallel execution of several instructions – superscalar processor
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