Question

Figure Q2 shows a state diagram for a synchronous sequential logic circuit with a state assignment table and input condition table as given below. Design the sequential logic circuit using D-type latches, assuming the behaviour for the unused states (ABC = 101, 110, 111) is not important. Show all your workings. State SO si S2 A 0 0 0 0 1 B 0 0 1 1 0 с 0 1 0 1 0 Input Condition IO 11 Z 0 1 S3 S4 b) Draw the simplest circuit diagram of your design in 2a). 6 c) Redraw the state diagram which accurately describes the behaviour of the circuit in 2b) including the unused states not shown in Figure Q2. 10 10 10 11 IO S4 SO 10 - . S1 S3 S2 11 11 11 11 Figure Q2​

Answer 1

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