Question

For a NAND-2 logic, if the widths of the pull down NMOS transistors are doubled, then assuming no change in the load capacitance, the high-to-low propagation delay (tpHL) for input vector (1,1) is

Answer 1

Answer:

4. Reduced by eight

Explanation:

Missing options in question are as below :-

1. Unchanged

2. Reduced by two

3. Increased by two

4. Reduced by eight

Answer :- 4. Reduced by eight

If wire width decreases,the high-to-low propagation delay ( tpHL ) for input vector (1,1) reduces by cube of reduction.