Question

Give further explanation about Net Initialization and regs.​

Answer 1

Explanation:

Hello;

At this moment, I can wrote some basic code in verilog , and I want now to know what is the difference between wire and reg to understand them , I read that wire is like real wire not stored data, but I can store data in wire (assign a = 1'b1) so could you please tell me how can i visually know how to understand that and put this idea in code?

thank you