Question

How interrupt controller is connected to cpu usage?

Answer 1

This diagram illustrates the structure of the interrupt controller. All potential external interrupt sources, except one, are routed through the interrupt controller, prioritised, and where not masked, result in a single interrupt request to the core. Two interrupt sources are treated differently by connection directly to the CPU generating a machine check exception. These are the software watchdog timer and interrupt request zero. The software watchdog timeout indicates a severe software problem, typically an endless loop or runaway code, requiring the processor to immediately stop normal operation and report or attempt to correct the error. The external interrupt request zero signal should be reserved for extreme errors that also require similar processor action to the software watchdog timeout. The remaining external inputs are controlled by the interrupt controller, and all can be masked. There is some control over relative priorities between all these inputs. Each external interrupt request is configurable to be edge triggered or active low. Similarly, the port C pins can also be selected to edge triggered or generate a request on any change in level. The inputs shown do not indicate any priority scheme, simply all those that can generate interrupt requests. These inputs are coming from the event registers of the controllers. Remember that they only generate an output if they are not masked, so the interrupt controller only recognizes unmasked requests. In some cases the input can reflect numerous events. There is only one input from each controller, so if that controller is capable of reporting more than one event, then work is involved in finding the original cause. When the CPU receives an interrupt request it initially only knows that it is an external interrupt request and so jumps to the external exception vector. It must then find out which of these inputs generated the request and then, in many cases, find the specific cause. The interrupt controller provides the means of determining which of these inputs generated the request.

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