How to obtain ballistic transport in a device?
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Well, by definition, ballistic transport occurs when the mean free path of the electrons is (much) larger than the device dimensions. That means that the electron will not scatter off of (lattice defects, impurities, phonons, surfaces, ...) while traversing the device.
Practical implementations of ballistic electron transistors have existed for some time now. The first that I recall used extremely pure epitaxial III-V layers and band gap engineering on either side to confine the carriers as a quasi-2D gas.
More recent efforts have looked at silicon MOS devices, where available feature sizes are small enough to allow ballistic transport. Often a SiGe drain layer is used, again to confine the carriers and reduce scattering.
Nanowires of various materials, and carbon nanotubes, are also being investigated.
In all cases, the focus is on transport in the drain or base - you will still have carrier mobility impacts on the larger circuit level.
Practical implementations of ballistic electron transistors have existed for some time now. The first that I recall used extremely pure epitaxial III-V layers and band gap engineering on either side to confine the carriers as a quasi-2D gas.
More recent efforts have looked at silicon MOS devices, where available feature sizes are small enough to allow ballistic transport. Often a SiGe drain layer is used, again to confine the carriers and reduce scattering.
Nanowires of various materials, and carbon nanotubes, are also being investigated.
In all cases, the focus is on transport in the drain or base - you will still have carrier mobility impacts on the larger circuit level.
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