Question

In tm4c123gh6pm mcu, the completion interrupt request from the dma controller is automatically cleared when the interrupt handler is

Answer 1

Answer:

Device wishing to perform DMA asserts the processors bus request signal.

Processor completes the current bus cycle and then asserts the bus grant signal to the device.

The device then asserts the bus grant ack signal.

The processor senses in the change in the state of bus grant ack signal and starts listening to the data and address bus for DMA activity.

The DMA device performs the transfer from the source to destination address.

During these transfers, the processor monitors the addresses on the bus and checks if any location modified during DMA operations is cached in the processor. If the processor detects a cached address on the bus, it can take one of the two actions:

Processor invalidates the internal cache entry for the address involved in DMA write operation

Processor updates the internal cache when a DMA write is detected