Question

in VLSI The carry chain in adder is consist with

Answer 1

Answer:

Introduction

Digital computer arithmetic is an aspect of logic design with the objective of developing

appropriate algorithms in order to achieve an efficient utilization of the available hardware [1-4].

Given that the hardware can only perform a relatively simple and primitive set of Boolean

operations, arithmetic operations are based on a hierarchy of operations that are built upon the

simple ones. Since ultimately, speed, power and chip area are the most often used measures of

the efficiency of an algorithm, there is a strong link between the algorithms and technology used

for its implementation.

High-speed Addition: Algorithms and VLSI Implementation:

First we will examine a realization of a one-bit adder which represents a basic building block for

all the more elaborate addition schemes.

Full Adder:

Operation of a Full Adder is defined by the Boolean equations for the sum and carry signals:

i i i i i i i i i i i i i i i i

s = a bc + a bc + a b c + a bc = a Åb Åc

i i i i i i i i i i i i i

c = a b c + a b c + a b c + a b c +1

Where: ai, bi, and ci are the inputs to the i-th full adder stage, and si and ci+1 are the sum and

carry outputs from the i-th stage, respectively.

From the above equation we realize that the realization of the Sum function requires two XOR

logic gates.

The Carry function is further rewritten defining the Carry-Propagate pi and Carry-Generate gi

terms:

i i i

p = a Åb , i i i

g = a ·b

At a given stage i, a carry is generated if gi is true (i.e., both ai and bi are ONEs), and if pi is true,

a stage propagates an input carry to its output (i.e., either ai or bi is a ONE). The logical

implementation of the full adder is shown in Fig. 1.a.