________ is a process of minimizing the total interconnect area used
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Answer:
In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements (such as transistors) together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and fabrication yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the semiconductor substrate, and the dielectric in between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication, interconnects are formed during the back-end-of-line after the fabrication of the transistors on the substrate.
Interconnects are classified as local or global interconnects depending on the signal propagation distance it is able to support. The width and thickness of the interconnect, as well as the material from which it is made, are some of the significant factors that determine the distance a signal may propagate. Local interconnects connect circuit elements that are very close together, such as transistors separated by ten or so other contiguously laid out transistors. Global interconnects can transmit further, such as over large-area sub-circuits. Consequently, local interconnects may be formed from materials with relatively high electrical resistivity such as polycrystalline silicon (sometimes silicided to extend its range) or tungsten. To extend the distance an interconnect may reach, various circuits such as buffers or restorers may be inserted at various points along a long interconnect.
Interconnect properties Edit
The geometric properties of an interconnect are width, thickness, spacing (the distance between an interconnect and another on the same level), pitch (the sum of the width and spacing), and aspect ratio, or AR, (the thickness divided by width). The width, spacing, AR, and ultimately, pitch, are constrained in their minimum and maximum values by design rules that ensure the interconnect (and thus the IC) can be fabricated by the selected technology with a reasonable yield. Width is constrained to ensure minimum width interconnects do not suffer breaks, and maximum width interconnects can be planarized by chemical mechanical polishing (CMP). Spacing is constrained to ensure adjacent interconnects can be fabricated without any conductive material bridging. Thickness is determined solely by the technology, and the aspect ratio, by the chosen width and set thickness. In technologies that support multiple levels of interconnects, each group of contiguous levels, or each level, has its own set of design rules.
Before the introduction of CMP for planarizing IC layers, interconnects had design rules that specified larger minimum widths and spaces than the lower level to ensure that the underlying layer's rough topology did not cause breaks in the interconnect formed on top. The introduction of CMP has made finer geometries possible.
The AR is an important factor. In technologies that form interconnect structures with conventional processes, the AR is limited to ensure that the etch creating the interconnect, and the dielectric deposition that fills the voids in between interconnects with dielectric, can be done successful. In those that form interconnect structures with damascene processes, the AR must permit successful etch of the trenches, deposition of the barrier metal (if needed) and interconnect material.
Interconnect layout are further restrained by design rules that apply to collections of interconnects. For a given area, technologies that rely on CMP have density rules to ensure the whole IC has an acceptable variation in interconnect density. This is because the rate at which CMP removes material depends on the material's properties, and great variations in interconnect density can result in large areas of dielectric which can dish, resulting in poor planarity. To maintain acceptable density, dummy interconnects (or dummy wires) are inserted into regions with spare interconnect density.
Historically, interconnects were routed in straight lines, and could change direction by using sections aligned 45° away from the direction of travel. As IC structure geometries became smaller, to obtain acceptable yields, restrictions were imposed on interconnect direction. Initially, only global interconnects were subject to restrictions; were made to run in straight lines aligned east–west or north–south. To allow easy routing, alternate levels of interconnect ran in the same alignment, so that changes in direction were achieved by connecting to a lower or upper level of interconnect though a via. Local interconnects, especially the lowest level (usually polysilicon) could assume a more arbitrary combination of routing options to attain the a higher packing density.