Laws of association y=50 sin(5000t) determine frequency
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The clear input is an asynchronous input, i.e. it doesn’t work in sync with the clock input, and the output (say, Q2 for second stage), will be set to zero as soon as clear input is activated.
Q2, which is an input for stage 3, will cause Q3 to pull down to zero at the very next PGT or NGT (depending on the type of flip flop used) of the clock, this in turn will cause Q4 to become zero as well.
Thus output of stage 4 will be a DC voltage of value 0V.
On the other hand, if clear input is deactivated before next clock transition, the output will be the divide by 16 output.
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