Question

Modern computers are based on the: (2) P-10 cycle (b) P- cycle​

Answer 1

Answer:

P-10 cycle

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Answer 2

Answer:

mark me brillianist please

Explanation:

The von Neumann architecture—also known as the von Neumann model or Princeton architecture—is a computer architecture based on a 1945 description by John von Neumann and others in the First Draft of a Report on the EDVAC.[1] That document describes a design architecture for an electronic digital computer with these components:

A processing unit that contains an arithmetic logic unit and processor registers

A control unit that contains an instruction register and program counter

Memory that stores data and instructions

External mass storage

Input and output mechanisms[1][2]

A von Neumann architecture scheme

The term "von Neumann architecture" has evolved to mean any stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the von Neumann bottleneck and often limits the performance of the system.[3]

The design of a von Neumann architecture machine is simpler than a Harvard architecture machine—which is also a stored-program system but has one dedicated set of address and data buses for reading and writing to memory, and another set of address and data buses to fetch instructions.

A stored-program digital computer keeps both program instructions and data in read–write, random-access memory (RAM). Stored-program computers were an advancement over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC. Those were programmed by setting switches and inserting patch cables to route data and control signals between various functional units. The vast majority of modern computers use the same memory for both data and program instructions, but have caches between the CPU and memory, and, for the caches closest to the CPU, have separate caches for instructions and data, so that most instruction and data fetches use separate buses (split cache architecture).