No of SRAM cells required for Y=AB+CD input LUT is_
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One of the features which make FPGA families differ from each other is their logic resource. For example, each CLB of Spartan-II FPGAs (PDF) is comprised of two slices, each with two LUTs. The Spartan 6 (PDF) has two slices with four LUTs each. Internally, LUTs comprise of 1-bit memory cells (programmable to hold either ‘0’ or ‘1’) and a set of multiplexers. One value among these SRAM bits will be available at the LUT’s output depending on the value(s) fed to the control line(s) of the multiplexer(s).
The number of inputs available for a LUT determine its size. In general, a LUT with n inputs is seen to comprise of 2n single-bit memory cells followed by a 2n:1 multiplexer or its equivalent (say, two 2n-1:1 muxes followed by one 2:1 mux).
A specific example of a 2-input LUT comprising of 4 SRAM bits and a 4:1 mux is as shown in Figure 2a. Next, Figure 2b shows its equivalent architecture but represents a 4:1 mux as a tree of 2:1 muxes.