Question

Problem #1 (static cmos logic): design a 3-input cmos nand gate (pun/pdn) with fan-out of 3. total output load of the nand gate is equal to 15ff and µn/µp = 2.5. for 0.35µm process technology tox = 7.6*10-9m, eox = 35*10-12f/m. compare the above design with that of a 3-input nor (pun/pdn) gate. state any benefits of one implementation over the other. for the sake of simplicity assume all capacitance is lumped and gate capacitance neglecting diffusion and wiring capacitance.

Answer 1

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