Q #1: Design a 16-bit memory of total capacity 8192 bits using SRAM chips of size 64 * 1 bit.
This design must allow both 8-bit and 16-bit word accesses. Give the array configuration of the
chips showing all required input and output signals for assigning this memory to the lowest address
space. Explain your mapped memory setup.
Answers
This design must allow both 8-bit and 16-bit word accesses. Give the array configuration of th
chips showing all required input and output signals for assigning this memory to the lowest ad
space. Explain your mapped memory setup.
[ 6.0 Mark
Q. # 2: A system using interrupt-driven IO that transfers data at an average of 8 KB/s on a
continuous basis is connected to a storage device
a. The interrupt processing time is about 100 ms (which includes the time to jump to the (ISR),
execute it, and return to the main program). Consider if the interrupt is for every byte, what porti
of processor time is used up by this I/O device.
[ 2.0 Marks]
b. Consider that the device has two buffers of 16-byte and it interrupts the microprocessor when
one of the two buffers is full. Logically, interrupt takes longer to process, as 16 bytes must be
transferred by the ISR. The processor
Answer:
For 16-bit mode, we will use the lower 13 bits of the address bus to select a single row, and the 7-bit column address bus to select the appropriate column(s) for the word being accessed. The word will be stored in the selected row.
Overall, this design allows for efficient use of the available SRAM chips and provides both 8-bit and 16-bit word access to the memory.
Explanation:
To design a 16-bit memory of total capacity 8192 bits using SRAM chips of size 64 * 1 bit, we need to use 128 SRAM chips in a 64 x 128 array configuration.
Each SRAM chip has a capacity of 64 bits, which can be thought of as a 64 x 1 bit array. To create a 16-bit memory, we need to combine 16 adjacent bits. Thus, we will combine every 16 bits from the 128 SRAM chips to form 8192 bits of memory.
The memory will be organized as follows:
Each row will contain 16 adjacent bits from each of the 128 SRAM chips, resulting in a total of 2048 rows.
Each column will contain a single bit from each of the 128 SRAM chips, resulting in a total of 128 columns.
The memory will be accessible through both 8-bit and 16-bit word accesses. In 8-bit mode, each byte will be stored in two adjacent rows, and in 16-bit mode, each word will be stored in a single row.
To allow for 8-bit and 16-bit word accesses, we need to use address lines to select the appropriate row(s) and column(s) for each access. Specifically, we need:
A 13-bit address bus to select the appropriate row(s), as 2^13 = 8192.
A 7-bit address bus to select the appropriate column(s), as we have 128 columns.
A read/write (R/W) signal to indicate whether the access is a read or write operation.
An enable signal to enable the memory for the duration of the access.
A data bus of 16 bits to transfer data to and from the memory.
For 8-bit mode, we will use the lower 13 bits of the address bus to select two adjacent rows, and the 7-bit column address bus to select the appropriate column(s) for the byte being accessed. The byte will be stored in the two selected rows.
For 16-bit mode, we will use the lower 13 bits of the address bus to select a single row, and the 7-bit column address bus to select the appropriate column(s) for the word being accessed. The word will be stored in the selected row.
Overall, this design allows for efficient use of the available SRAM chips and provides both 8-bit and 16-bit word access to the memory.
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