Question

Q.2
The chip select logic for a certain DRAM chip in a memory system design is shown below.
Assume that the memory system has 16 address lines denoted by Ais to Ao. What is the range
of addresses (in hexadecimal) of the memory system that can get enabled by the chip select
(CS) signal?
Als
Aja
ALI
D
CS
A12
Au
(A) C800 to CFFF
(C) C800 to C8FF
(B) CA00 to CAFF
(D) DA00 to DFFF​

Answer 1

Answer:

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