Question

Q2 (8 pts): Consider a cache-DRAM interface. One cache line is 128
B. The cache can fetch a complete line from the DRAM in a
maximum of 100 cycles. The DRAM has a dataOut port of 16 bits
and acts as a pipeline of latency L and cycle
time of 1 cycle,
hence
outputting 16 b/cycle when the pipo fills up. What is Loqual to?​

Answer 1

Answer:

I m also trying this question, on Chegg..