Question

Rs latch nand and nor based using multisim and verilog software

Answer 1

Answer:

Analog circuit's process signals with continuous variation of voltage. .... NAND GATE: The NAND gate is a contraction of AND-NOT. ... Write the Verilog /VHDL code for a half adder

Answer 2

Heya mate.....

SR latch is a gated set-reset latch. The S and R inputs control the state of the latch when a HIGH level is applied to the EN input. 

Hope this will help you....